In data processing systems, interrupts are used to signal a processor that an interrupt condition exists at a given source. This interrupt source could be, for example, an adapter card on a system bus which requires some type of service. The required service may be to initiate a transfer of data or to read a status register that has recently changed.
When the processor has been conditioned to accept an interrupt, otherwise known as having the interrupts enabled, the processor will initiate interrupt processing upon the receipt of the interrupt. This interrupt processing typically involves the processor interrogating the source of the interrupt, performing functions based upon the type of interrupt, and resetting/turning off the interrupt.
Interrupt priorities have also been accommodated in traditional systems. If more than one interrupt signal is active at a given time, the use of interrupt priorities tells the processor which interrupt to service first.
Interrupt controllers have been designed to offload certain interrupt handshake functions that are required, such as resetting an interrupt signal. Typical of such interrupt controllers is an Intel 8259 controller, which is described in the Intel Component Data Catalog, 1988 (available from Intel Corp. Literature Department, 3065 Bowers Avenue, Santa Clara, Calif.), and hereby incorporated by reference as background material. These interrupt controllers can monitor multiple interrupt sources and only interrupt the processor using a single interrupt line.
Current interrupt signalling methods were primarily designed for uniprocessor systems with few interrupt sources or priority levels. Most systems send interrupts over one or more interrupt lines hardwired on the planar. In a multiprocessor environment, where there is more than one processor capable of servicing an interrupt, these types of interrupt signalling techniques cause increases in bus complexity. An interrupt signal from each interrupt source would have to be wired to each processor or interrupt controller capable of servicing such interrupt.
Attempts to satisfy needs of a multiprocessing data processing system have required dedicated interrupt controllers for each processor in the system. This approach is not only costly but also does not allow for cohesive management of interrupts which are generated from a plurality of sources that must be routed to a plurality of processors for servicing.
A method is needed that is expandable, allowing many interrupt sources and priority levels. In addition, a method of signalling interrupt information is needed for use with multiprocessing systems that handle multiple processors and multiple interrupt controllers.
Current interrupt systems are hardware specific, with varying amounts of software dependencies. A change in the number or types of interrupts requires changes be made to the particular operating system software. An interrupt subsystem is needed that provides software independence from the underlying hardware interrupt structure.
An example of a prior art system which solves many of the problems identified above is U.S. patent application Ser. No. 08/573,918(which is a continuation of Ser. No. 08/124,182) for "Scalable System Interrupt Structure For A Multi Processing System".
However, the prior art systems do not solve the problem addressed and solved by the present invention whereby interrupts are signalled from I/O devices by means of interrupt packets sent to interrupt processing or routing logic where the packets are accepted or rejected by the routing logic according to priority and rejected interrupts are queued in I/O control logic for resending when signalled by an interrupt reissue signal.